1. Field of the Invention
The present invention generally relates to methods of manufacturing semiconductor devices and systems for manufacturing semiconductor devices, and particularly relates to a method of and system for manufacturing a MOS-type (metal-oxide-silicon type) field effect transistor capable of high speed operation.
2. Description of the Related Art
In a related-art process for manufacturing a MOS-type field effect transistor (MOSFET), an impurity element is injected as a dopant by use of an offset spacer as a mask to form an extension region in order to reduce offset capacitance between the gate and the source or between the gate and the drain. The offset spacer is made by forming an insulating film that covers the silicon substrate and the multilayer gate structure, followed by performing an etchback by use of the RIE (reactive ion etching) method or the like so as to leave only a portion of the insulating film flanking the side walls of the multilayer gate structure. The offset spacer serves to create the extension region such that the profile of the extension region on the gate side is spaced apart from the edge of the gate. This ensures that the extension region does not extend in the horizontal direction after an activating heat treatment to end up existing directly below the gate.
In recent years, size reduction in MOSFETs has been further pursued in order to improve the circuit density and operation speed of the MOSFETs. Together with the size reduction in MOSFETs, it is also required to further suppress a horizontal extension of the extension region. Especially when the extension region is formed deep, its horizontal extension tends to be large, which necessitates the control of the extension region so as to make it extremely shallow. Because of this, the energy for injecting impurity ion is now sometimes set below 1 KeV.
As the extension region is formed shallow in the silicon substrate, with a dry etching performed based on the RIE method at the time of forming an offset spacer, an energy for pulling ion into the silicon substrate is about the same as the energy for injecting impurity ion, resulting in the depth of an affected layer being substantially the same as the depth of the extension region. In this case, the crystalline quality of the surface of the silicon substrate may affect the electrical characteristics of the MOSFET.
[Patent Document] Japanese Patent Application Publication No. 2001-326347
There are large number of dry etching apparatuses used in the manufacturing of MOSFETs. These dry etching apparatuses have varying etching characteristics. In general, the high-frequency power of a dry etching apparatuses is set to the same predetermined value for a plurality of dry etching apparatuses when the same process is supposed to be performed. When the state of sediments in the apparatuses varies through continuous running and maintenance work, however, a mixture ratio of process gasses and/or ion density may change due to the mixing of the sediments. This causes the electric current running between electrodes to change, resulting in a change in the voltage that pulls etching ion into the substrate. When the voltage that pulls etching ion into the substrate increases, for example, the affected layer formed in the silicon substrate reaches a further depth. Due to such factors, the depth of the affected layer formed in the silicon substrate varies between the dry etching apparatuses. The affected layer is believed not to contribute to carrier conduction, so that the depth of the extension region largely contributing to the carrier conduction may end up having variation between silicon substrates. This gives rise to a problem in that the electrical characteristics of the MOSFETs such as on-resistance and threshold voltage may vary.
Accordingly, there is a need for a method of manufacturing semiconductor devices in which variation in electrical characteristics such as on-resistance between semiconductor substrates is suppressed. There is also a need for a system for manufacturing semiconductor devices in which variation in electrical characteristics such as on-resistance between semiconductor substrates is suppressed.